Non-contact etch annealing of strained layers

ABSTRACT

The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/484,181; filed Jun. 30, 2003, and is a continuation-in-part of U.S.application Ser. No. 10/264,393, filed Oct. 4, 2002.

FIELD OF THE INVENTION

Embodiments of the present invention relate to controlling the growthand morphology of surface roughness during an annealing and relaxationprocess of strained films, and more particularly to decreasing surfacecrystalline dislocations during a relaxation process.

BACKGROUND OF THE INVENTION

In the conventional art, many semiconductor device fabrication processesutilize planar surfaces. Furthermore, as semiconductor fabricationtechnology progresses, increasing carrier mobility and decreasinglattice dislocation density become increasingly critical. Improvingdevice yields by reducing dislocations provides for improvedmanufacturing efficiencies and cost.

In the conventional art, a silicon layer is used as the active devicemedium upon which semiconductor devices are fabricated. Single-crystalsilicon has a specific carrier mobility value that is fundamental to thematerial. The mobility value is a key parameter in many activesemiconductor devices. Often, it is desired to enhance or increase thedevice carrier mobility value to increase the switching speed andtherefore the performance of the fabricated devices such as transistors.Because of the many fundamental and specific advantages in utilizingsilicon as the semiconductor material, it is highly desirable to adoptmethods to enhance silicon mobility instead of utilizing higher mobilitymaterials that are harder to process such as Germanium or GalliumArsenide.

One practical method of enhancing silicon mobility is by straining thesilicon layer. By placing the active silicon under tension,significantly higher mobility resulting in higher device switching speedand drive currents can be achieved.

A method of generating such tensile strained silicon involves growingthe silicon layer epitaxially above a relaxed silicon germanium film ofa specific composition. This effect occurs because the silicon latticeconstant, about 5.43 Angstroms, is smaller than the lattice constant ofa fully relaxed silicon germanium alloy film. Such alloys can beengineered to have a lattice spacing linearly varying from 5.43Angstroms (100% silicon) to 5.65 Angstroms (100% germanium). For thepure germanium film, the lattice spacing is about 4% larger than puresilicon. Thus for example, a Si_(0.75)Ge_(0.25) alloy (25% germaniumcontent) would have a lattice constant about 1% larger than silicon.

The strained silicon film could therefore be advantageously fabricatedby epitaxially growing the device silicon film on a relaxed siliconGermanium (SiGe) alloy film of the requisite composition.

A fundamental complication of this mobility enhancement approach is therequirement of a relaxed SiGe film. If the SiGe film is grown onto abase silicon wafer, the film will first grow in a lattice-matched manneras a compressive layer. This means that the SiGe alloy will becompressed to the natural silicon lattice spacing and will be strained.Since the function of the alloy film requires a relaxation of thecompressive strain, there must be a step where the SiGe alloy is relaxedto its unstrained state. Such a step necessarily introduces numerousdislocations in the SiGe layer to accommodate the lattice spacing andvolume increase. The film also usually “buckles” and roughenssignificantly during this relaxation process.

The major parameters characterizing a practical relaxed SiGe alloy filminclude the amount that the film has been relaxed from its strainedstate (i.e. 50% relaxation would mean that the film has relaxed half ofits strain), the roughness of the film, and the dislocation defectdensity that would be affecting the subsequent growth of the strainedsilicon device film.

The surface dislocation density is a critical parameter affecting theelectrical properties of semiconductor materials since they are highlydependent upon crystalline defects. Dislocations can comprise insertionof an extra half-plane of atoms into a regular crystal structure,displacement of whole rows of atoms from their regular lattice position,and/or displacement of one portion of the crystal relative to anotherportion of the crystal. Dislocations present on the device layer cantend to short-circuit p-n junctions and also scatter electrons in auniform n-type crystal, impeding their motion and reducing theirmobility. Dislocations also cause highly localized distortion of thecrystal lattice leading to the formation of “trapping” sites where therecombination of positive (holes) and negative (electrons) carriers isenhanced. This may cause, for example, the electrons from the n-p-ntransistor emitter to recombine with holes in the p-type base regionsbefore they can be collected at the n-type collector region, reducingthe transistor current gain. This electron “lifetime” may besignificantly reduced by recombination when as few as one out of 10¹¹atoms/cm3 of silicon are removed from their normal lattice sites.Although some dislocations can be removed from a semiconductor materialby thermal annealing, many dislocations are permanent and thermallystable. Many of the relaxation approaches are therefore tuned tominimize the defect density of the type that can be translated to thedevice layer and cause device performance degradation, failure and yieldlosses.

In one method according to the conventional art, the SiGe alloy is grownwith a slowly varying grade from 0% germanium to the required alloycomposition at a sufficiently low temperature to grow a dislocation freeinitial film and through subsequent annealing, the slow gradient helpsto accommodate film relaxation through the generation of dislocationsthat are buried within the SiGe layer. This technology is explained inLegoues & al. (U.S. Pat. No. 5,659,187 “Low defect density/arbitrarylattice constant heteroepitaxial layers”). To limit the production ofdislocations threading to the surface, the SiGe grade is usually lessthan 2% composition increase per 1000 Angstroms of SiGe film growth.This shallow gradient approach is lower in productivity due to itsrelatively thick SiGe layer composition and may require numerousgrowth/anneal cycles to achieve roughness and dislocation goals.

In yet another method according to the conventional art, the surfaceroughness or the SiGe alloy layer can be reduced using a chemicalmechanical polishing (CMP) process such as taught by Fitzgerald (U.S.Pat. No. 6,291,321 “Controlling threading dislocation densities in Ge onSi using graded GeSi layers and planarization” and U.S. Pat. No.6,107,653, “Controlling threading dislocation densities in Ge on Siusing graded GeSi layers and planarization”). CMP utilizes a combinationof vertical force between a wafer and an abrasive pad as well as achemical action of a slurry, to polish the surface of the wafer to ahighly planar state. The roughness of the resulting semiconductorsurface can typically be reduced to approximately 1 Angstrom RMS whenmeasured by an Atomic Force Microscope (AFM). However, CMP is relativelycostly as a result of the slurry and the amount of time it takes toperform the process. Furthermore, the CMP process does not generallyreduce the dislocation density in the wafer. Finally, this lineargrowth/anneal/CMP sequence is costly as it requires numerous sequentialprocess and wafer handling steps.

Another method uses miscut wafers to help the grown film to relax asmuch as possible and accommodate the lattice mismatches. See for exampleFitzgerald & al. (U.S. Pat. No. 6,039,803, “Utilization of miscutsubstrates to improve relaxed graded silicon-germanium and germaniumlayers on silicon”) that teaches the improvement of using base wafershaving 1 to about 8 degrees of miscut from a true [100] orientation tohelp grow a less defective, relaxed layer of a second semiconductormaterial. Although the base substrate miscut can improve the relaxeddefect density to some extent, the improvements are generally consideredinsufficient for leading edge applications.

Referring to FIG. 1, a flow diagram of a process according to theconventional art is shown. This process produces a relaxed film of SiGealloy material by first growing a strained film on a base wafer 110,subjecting the strained film to an anneal step to relax the film andconcurrent generation of surface roughening (buckling) and dislocations120, followed by a planarization smoothing step such as CMP 130. The useof an epitaxial step such as CVD (Chemical Vapor Deposition) or MBE(Molecular Beam Epitaxy) followed by a planarization step such as CMPsignificantly complicates the film relaxation preparation process sincemultiple equipment, cleans, and wafer handling are required. This inturn would increase the manufacturing cost of the relaxed filmfabrication process.

Referring now to FIGS. 2A-2C, various sectional views of a semiconductorlayer are shown to illustrate the anneal/CMP conventional art such asdisclosed by Fitzgerald in more detail. As depicted in FIG. 2A, a singlecrystalline semiconductor surface formed by an epitaxial process whereina strained SiGe film 210 is grown onto a base silicon wafer 220. Thesemiconductor layer is comprised of single crystalline silicon-germaniumhaving a surface roughness 230 of approximately 1-2 Angstrom RMS. Thesilicon-germanium layer typically was grown at a sufficiently lowtemperature where the film is supercritically stressed but no relaxationhas taken place. The dislocation defect density 240 is therefore verylow, on the order of 1 dislocations/cm² or less.

As depicted in FIG. 2B, an anneal is performed on the substrate to relaxthe SiGe alloy film which generates substantial surface roughening 250and dislocation defects 260. The resulting surface may have a buckledroughening 250 exceeding 200-300 Angstroms RMS and a dislocation defectdensity 260 exceeding approximately 10⁷ dislocations/cm².

As depicted in FIG. 2C, a separate CMP process generally reduces surfaceroughness 270 to approximately 1-5 Angstroms RMS. However, the CMPprocess generally does not decrease dislocations 260 in thesilicon-germanium layer 310 and must be accompanied by comprehensiveclean processes.

Thus, the conventional art is disadvantageous in that planarizingprocesses are relatively costly and time-consuming processes. Theconventional art also suffers from relatively high levels ofdislocations. A better and less costly approach that can fully relaxstrained SiGe alloy films while controlling surface roughness anddislocation defect levels is highly desirable.

SUMMARY OF THE INVENTION

A method for etch annealing a semiconductor layer is disclosed. Inaddition to its significant effect in controlling the roughnessincreases during the relaxation process, the method has the unexpectedbenefit of substantially reducing dislocations. The reduced dislocationdensity is advantageous in that carrier mobility and yield areincreased.

In one embodiment, a method of forming a strained semiconductor layer isprovided. The method comprises growing a strained first semiconductorlayer, having a graded dopant profile, on a wafer, having a firstlattice constant. The dopant imparts a second lattice constant to thefirst semiconductor layer. The method further comprises growing astrained boxed second semiconductor layer having the second latticeconstant on the first semiconductor layer and growing a sacrificialthird semiconductor layer having the first lattice constant on thesecond semiconductor layer. The method further comprises etch annealingthe third and second semiconductor layer, wherein the thirdsemiconductor layer is removed and the second semiconductor layer isrelaxed. The method may further comprises growing a fourth semiconductorlayer having the second lattice constant on the now relaxed secondsemiconductor layer, wherein the fourth semiconductor layer is relaxed,and growing a strained fifth semiconductor layer having the firstsemiconductor lattice constant on the fourth semiconductor layer. Themethod controls the surface roughness of the semiconductor layers. Themethod also has the added benefit of reducing dislocations in thesemiconductor layers.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not by way oflimitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 shows a flow diagram of a conventional art process forcontrolling the surface roughness and dislocations of a semiconductormaterial.

FIG. 2A shows a sectional view of a strained semiconductor layer havingan initial surface roughness, according to the conventional art.

FIG. 2B shows a sectional view of a relaxed semiconductor layer having asubstantially higher surface roughness and dislocation density after anannealing step, according to the conventional art.

FIG. 2C shows a sectional view of a semiconductor layer having a planarsurface after a CMP process is performed on the conventionally annealedsurface, according to the convention art.

FIG. 3 shows a flow diagram of a process for controlling the surfaceroughness and reducing dislocations of a strained semiconductor layer,in accordance with one embodiment of the present invention.

FIGS. 4A-4B show sectional views of a strained semiconductor structurehaving reduced surface roughness and reduced dislocations, in accordancewith one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone of ordinary skill in the art that the present invention may bepracticed without these specific details. In other instances, well-knownmethods, procedures, components, and circuits have not been described indetail as not to unnecessarily obscure aspects of the present invention.

Referring to FIG. 3, a flow diagram of a process for controlling thesurface roughness and reducing dislocations of a strained semiconductorlayer, in accordance with one embodiment of the present invention, isshown. As depicted in FIG. 3, the process begins with growing a strainedgraded first semiconductor layer, on a wafer, at 310. The wafercomprises a semiconductor having a first lattice constant. The strainedgraded first semiconductor layer comprises a semiconductor having agraded dopant profile, wherein the dopant imparts a second latticeconstant. The first lattice constant is less than the second latticeconstant. The term “lattice constant” is intended to mean the latticestructure in a normally relaxed single crystalline state.

In one implementation, the strained graded first semiconductor layercomprises a strained SiGe alloy having a graded doping profile. Thestained graded SiGe layer of approximately 4000-20,000 angstroms (Å) isformed by an epitaxial deposition process. The doping profile of thegermanium (Ge) increases from approximately 0% at the wafer to 25% atthe surface of the strained SiGe layer. In one implementation, theepitaxial deposition process is performed in a hydrogen-chloride (HCl)ambient. The as-grown strained graded SiGe layer has a roughness ofapproximately 2 Angstroms root-mean-square (RMS), and less thanapproximately 1 dislocations/cm².

At 320, a strained boxed second semiconductor layer is grown on thestrained graded first semiconductor layer. The strained boxed secondsemiconductor layer is grown having the second lattice constant. Theterm “boxed” is intended to indicate that the doping profile of thelayer is substantially constant. The roughness of the strained boxedsecond semiconductor layer is low because the as-grown semiconductor isclose to being or is fully strained and has not been subjected tothermal cycles that would have started the relaxation process. In oneimplementation, the strained boxed second semiconductor layer comprisesa strained SiGe layer having a constant Ge doping profile. The strainedboxed SiGe layer of approximately 500-5000 Å is formed by an epitaxialdeposition process. The doping profile of the Ge is approximately 25%throughout the first strained boxed SiGe layer. In one implementation,the epitaxial process if performed in an HCl ambient.

At 330, a sacrificial third semiconductor layer is grown on the strainedboxed second semiconductor layer. The sacrificial third semiconductorlayer is grown having the first lattice constant. In one implementation,the sacrificial third semiconductor layer comprises a silicon (Si)layer. The sacrificial Si layer of approximately 100-300 Å is formed byan epitaxial deposition process. It is also appreciated that the growthof the sacrificial third semiconductor layer may be omitted.

At 340, an etch anneal is performed upon the sacrificial thirdsemiconductor layer and the boxed second semiconductor layer. Thesurface is “etch annealed” utilizing, for example, an epitaxial chambersubjecting the wafer to a high temperature anneal in an etching ambient.The etch anneal etches away the sacrificial third semiconductor layer,formed at 330, and relaxes the boxed strained second semiconductorlayer, formed at 320. The etch anneal may also relax the graded strainedfirst semiconductor layer, formed at 310. This etch anneal produces asmoother surface than a simple anneal performed in a non-etchingambient.

A similar process has been shown to smooth unstrained films in a processreferred to as an “epi-smoothing” process. The epi-smoothing process isdisclosed in U.S. Pat. No. 6,287,941, granted Sep. 11, 2001, entitled“Surface Finishing of SOI Substrates Using an EPI Process,” which isincorporated by reference herein. Since the etching process applied torelaxing strained films controls the overall roughness rather thansmooths the surface, it will hereinafter called “etch annealing”.

In one implementation, the etch annealing process comprises subjectingthe sacrificial Si layer to an etchant including a halogen bearingcompound such as HCl, HF, HI, HBr, SF₆, CF₄, NF₃, CCl₂F₂, or the like.The etch annealing process is performed at an elevated temperature of700-1200° C., or greater. For example, the surface of the sacrificial Silayer and the strained boxed SiGe layer is exposed to a HCl containinggas, at an elevated temperature of 700-1200° C., in an etch annealingprocess, such that:SiGe(solid)+4HCl(gas)→SiCl₄(gas)+2H₂(gas)+GeThis process is substantially the reversal of an epitaxial depositionprocess for growing a silicon-germanium layer. The difference being thatif the concentration of hydrogen chloride is too high, the surface isetched instead of silicon-germanium being deposited. The etch annealingprocess removes silicon and silicon-germanium concurrently with thestrain relaxation process and has been shown to help mitigate theundesirable emergence of dislocations and surface roughening. Thus, theetch annealing process acts to control surface roughening and lowerdislocation density while achieving substantially complete filmrelaxation.

Accordingly, the etchant removes the sacrificial Si layer. Furthermore,the concurrent use of the etchant and a temperature sufficient to relaxthe strained boxed SiGe or the strained boxed SiGe and strained gradedSiGe layers has been found to help reduce or eliminate the generation ofdislocations with a concurrent reduction in relaxation roughening of thesurface. This favorable effect is believed linked to a reduction of thestress inducing cycloidic cusp tips present during a non-etch anneal (H.Gao & W. D. Nix, “Surface Roughening of Heteroepitaxial Thin Films”,Annu. Rev. Mater. Sci. 1999, 29, pg. 173-209). In the work by Gao andNix, it is explained that the strain caused by the lattice mismatchdrives the generation of an undulating profile on the surface that hasperiodic sharp cusp tips that favor the creation of dislocations atthese highly stressed locations. The concurrent etching process duringlattice relaxation is believed to significantly blunt or round the cusptips that reduce the stress concentration and thus reduces the surfacedislocation density by affecting its creation kinetics. The surfaceroughening is also disfavored by the etch ambient.

The etch annealing process may be performed at a range of elevatedtemperatures that would favor the concentration of the dislocations awayfrom the surface to relax the lattice structure of the boxed SiGe layer.The thermal treatment may be from a resistance heater, RF heater, highintensity lamps, or the like. The thermal treatment means should becapable of heating the semiconductor material at a rate of approximately10-20° C./sec, or more.

Because the strained graded SiGe layer, strained boxed SiGe layer, andthe sacrificial Si layer are performed within an epitaxial reactor andthe etch annealing is also performed within the same system, repetitionof these steps is straightforward and the general economy of the processcan be fully appreciated since no cleans, external anneals or CMPplanarization steps are needed.

The etch annealing process removes strained semiconductor material in amanner that blunts sharpening (roughening) features that form on thesurface upon film relaxation. The rate of etching is a function of time,temperature, and the etchant type and concentration. Therefore,controlling these parameters during the etch annealing process controlsthe amount of etching. The etch annealing process is performed until theprocess reduces surface roughness by approximately fifty percent or morecompared to an anneal without the etchant. Thus, the etch annealingprocess acts to control surface roughening during film relaxationsufficient for subsequent semiconductor device fabrication processes.The method also provides the added benefit of reducing dislocations byup to two orders of magnitudes or more.

Furthermore, unlike convention CMP processes that are limited toremoving a few tens of nano-meters or less, the etch annealing processcan be used to remove as much as a few hundreds of nano-meters or moreof semiconductor material.

It is also appreciated that the etch anneal may be performed partwaythrough the growth of the strain graded first semiconductor layer formedat 310. Furthermore, the etch anneal may be performed more than once atduring various processes, such as 310, 320 and/or 330.

At 350, a boxed fourth semiconductor layer is grown on the relaxed boxedsecond semiconductor layer. The boxed fourth semiconductor layer isgrown having the second lattice constant and has a relaxed structure. Inone implementation, the boxed fourth semiconductor layer comprises arelaxed SiGe layer having a constant Ge doping profile. The boxed SiGelayer of approximately 1000-10,000 Å is formed by an epitaxialdeposition process. The doping profile of the Ge is approximately 25%throughout the boxed SiGe layer. In one implementation, the epitixialprocess if performed in an HCl ambient.

At 360, a fifth semiconductor layer is grown on the boxed fourthsemiconductor layer. The fifth semiconductor layer is grown having thefirst lattice constant. Accordingly, the fifth semiconductor layer isformed as a strained semiconductor layer. In one implementation, thefifth semiconductor layer comprises a silicon (Si) layer. The second Silayer of approximately 100-200 Å is formed by an epitaxial depositionprocess.

The fifth semiconductor layer may be utilized for fabricating additionallayers thereupon or device regions therein. The reduced dislocationdensity of the resulting strained fifth semiconductor layeradvantageously results in higher carrier mobility. The higher carriermobility improves characteristics of devices, such as field effecttransistors, bipolar transistors, and the like.

Referring now to FIGS. 4A-4B, sectional views of a strainedsemiconductor structure having reduced surface roughness and reduceddislocations, in accordance with one embodiment of the presentinvention, is shown. As depicted in FIG. 4A, an intermediatesemiconductor structure comprises a wafer 410. A strained graded firstsemiconductor layer 420 is formed upon the wafer 410. A strained boxedsecond semiconductor layer 430 is formed upon the strained graded firstsemiconductor layer 420. A sacrificial third semiconductor layer 440 isformed upon the strained boxed second semiconductor layer 430.

As depicted in FIG. 4B, the strained semiconductor structure after anetch anneal process is shown. The graded first semiconductor layer 420and the boxed second semiconductor layer have been relaxed by the etchanneal process. The sacrificial third semiconductor layer 440 has beenremoved. A boxed fourth semiconductor layer 450 is formed upon therelaxed boxed second semiconductor layer 430 and is relaxed. A fifthsemiconductor layer 460 is formed upon the relaxed boxed fourthsemiconductor layer 450. The fifth semiconductor layer 460 has a firstlattice constant, and the relaxed boxed fourth semiconductor layer 450has a second lattice constant. Therefore, the fifth semiconductor layer460 comprises a strained semiconductor layer.

The etch annealing process yields a less costly alternative than theconventional art by allowing for a usable strained silicon device layerwithout costly external planarization steps. Furthermore, one skilled inthe art would expect that etch annealing would not affect the generationof the dislocation process. However, the etch annealing process resultsin the unexpected benefit of decreasing the dislocation density toapproximately 10⁵ dislocations/cm², as compared to an anneal madewithout an etch ambient of approximately 10⁷ dislocations/cm². The etchannealing process is also highly effective in fully relaxing the film,rendering it suitable as a base to grow a strained silicon device film.

The resulting strained fifth semiconductor layer 460 can be utilized forfabricating semiconductor layers thereupon or device regions therein.The reduced dislocation nature of the semiconductor layer advantageouslyresults in higher carrier mobility. The high carrier mobility in thefifth semiconductor layer 460 improves characteristics of the devicesformed therein.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the art to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the Claims appended hereto and theirequivalents.

1-15. (canceled)
 16. A method comprising: forming over a strainedsemiconductor layer having a lattice constant, a second strainedsemiconductor layer also having the lattice constant; forming asacrificial semiconductor layer having a second lattice constant on saidsecond semiconductor layer; annealing the sacrificial semiconductorlayer and the second strained semiconductor layer in an etching ambientto remove the sacrificial semiconductor layer and reduce strain in asecond semiconductor layer; forming a relaxed semiconductor layer havingthe lattice constant on the second semiconductor layer; and forming athird strained semiconductor layer having the lattice constant on therelaxed semiconductor layer.
 17. The method of claim 17 wherein at leastone of the strained semiconductor layer, the second strainedsemiconductor layer, the sacrificial semiconductor layer, the relaxedsemiconductor layer, and the third strained semiconductor layer areformed by epitaxial deposition of graded silicon germanium.
 18. Themethod of claim 17 wherein the epitaxial deposition is performed in ahydrogen-chloride ambient.
 19. The method of claim 16 furthercomprising: providing a substrate having the second lattice constant;and forming the strained semiconductor layer with a graded dopantprofile on the substrate.
 20. The method of claim 19 wherein the gradeddopant profile imparts the lattice constant to the strainedsemiconductor layer.
 21. The method of claim 16 wherein the etchingambient comprises a halogen bearing etchant.
 22. The method of claim 21wherein said halogen bearing etchant is hydrogen chloride.
 23. Themethod of claim 21 wherein said halogen bearing etchant is hydrogenfluoride.
 24. The method of claim 21 wherein etching ambient furthercomprises hydrogen.
 25. The method of claim 21 wherein the annealingincreases a temperature of the sacrificial semiconductor layer. tobetween about 700-1200° C.
 26. A method of controlling the surfaceroughness of a strained semiconductor material comprising: forming afirst strained semiconductor layer having a graded dopant profile on awafer having a first lattice constant, the dopant imparting a secondlattice constant to the first semiconductor layer; forming a secondstrained semiconductor layer having said second lattice constant on thefirst semiconductor layer; forming a sacrificial semiconductor layerhaving the first lattice constant on the second semiconductor layer; andetch annealing the third and second semiconductor layer, wherein saidthird semiconductor layer is removed and said second semiconductor layeris relaxed.
 27. The method of claim 26 wherein the etch annealingcomprises exposing the third semiconductor layer to an etch ambientcomprising a halogen bearing etchant.
 28. The method of claim 27 whereinsaid halogen bearing etchant is hydrogen chloride.
 29. The method ofclaim 27 wherein said halogen bearing etchant is hydrogen fluoride. 30.The method of claim 26 wherein etch annealing said surface of the thirdsemiconductor layer further comprises exposing the third semiconductorlayer to hydrogen.
 31. The method of claim 26, wherein etch annealingsaid third semiconductor layer further comprises increasing atemperature of said third semiconductor layer. to between 700 and 1200degrees Celsius.
 32. The method of claim 26 wherein at least one of thefirst strained semiconductor layer, the second strained semiconductorlayer, and the sacrificial semiconductor layer are formed by epitaxialdeposition of graded silicon germanium.
 33. The method of claim 32wherein the epitaxial deposition is performed in a hydrogen-chlorideambient.
 34. A method of reducing dislocations in a semiconductormaterial comprising relaxing a strained semiconductor layer having afirst lattice constant by etch annealing to remove an overlyingsacrificial semiconductor layer having a second lattice constant, thestrained semiconductor layer formed over a second strained secondsemiconductor layer having a second lattice constant imparted by agraded dopant profile.
 35. The method of claim 34 wherein the etchannealing comprises exposing the strained semiconductor layer and thesacrificial semiconductor layer to an etch ambient comprising a halogenbearing etchant.
 36. The method of claim 34 wherein said halogen bearingetchant is hydrogen chloride.
 37. The method of claim 34 wherein saidhalogen bearing etchant is hydrogen fluoride.
 38. The method of claim 34wherein the etch annealing further comprises exposing the strainedsemiconductor layer and the sacrificial semiconductor layer to hydrogen.